The present invention relates to error detection, and more particularly, to error detection and recovery from soft failures of data read from a memory shared by two processors.
Traditionally, error detection and correction (EDAC) techniques of data read from a memory, require the storage into a memory unit of an additional number of bits which is a function of the number of bits composing the information and the resolution capacity of these additional bits (i.e., commonly known as syndrome bits). Each time information (word/byte) is written into memory, the corresponding syndrome bits must be generated. When information is read from memory (in parallel with the corresponding syndrome bits) and an error is detected, the error can generally be corrected, i.e., if the nature of the error is within the resolution capacity of the syndrome bits. This method requires a considerable amount of additional hardware and requires extra time to perform the correction. When the extra time is not available to a processor accessing the memory, a new scheme must be utilized to perform the correction i.e., recovery scheme.
Thus, there is provided by the present invention an approach to error detection and correction which essentially does not require any extra time.